硅与非硅材料“混搭”难题解决

3D-Transistor Array Based on Horizontally Suspended Silicon Nano-bridges Grown via a Bottom-Up Technique

Jin Yong Oh, et al

Self-assembled semiconductor nanowires, prepared by bottomup techniques, are touted to be promising building blocks for future nanodevices because they have inherently small dimensions as well as wide choices of materials and compositions. They have been employed in fabrication of a wide range of nanodevices such as fi eld-effect-transistors (FETs), photovoltaic devices, light-emitting-diodes, photodetectors, and sensors. Among various kinds of self-assembled nanowires, silicon (Si) nanowires have been actively studied with an aim of bearing the next generation FETs whose feature sizes will be smaller than a few tens of nanometer. In most cases, selfassembled Si nanowire based FETs have been fabricated via pick-and-place or drop-cast techniques because randomly oriented, self-assembled nanowires present an alignment challenge. For creating nanowire devices, the conventional protocols harvest nanowire ensembles from growth substrates and disperse them on device substrates, and therefore, rigorous alignment processes are required to prepare arrays with these randomly oriented and distributed nanowires. These fabrication techniques, therefore, are incompatible with large integration of devices due to lacks of reproducibility and fidelity.